ASIC Design Engineer (SoC)

NovuMind is a startup co-located in Silicon Valley and Beijing. Our mission is to eliminate the existing barriers of artificial intelligence deployment, so that companies of all sizes, in all industry sectors, can unleash the full power of AI. Centered around our AI chip, our full stack solutions of deep learning enable AI in products and services from embedded to cloud. We are looking for an ASIC Design Engineer (SOC) in our Santa Clara, CA office.

Duties & Responsibilities

• Responsible for System on Chip (SoC) logic design. Design microprocessor, memory controller, on-chip interconnect, power and real time controller, interface and IP sub-systems. Perform sub-system and chip level integration.
• Perform micro architecture design/specification, RTL development and integration.
• Perform linting checks, simulation, clock domain crossing check, synthesis and debug timing, at module level and chip level. Perform conformal low power check and formal verification (Logic Equivalence Checking).
• Work with system architects on performance analysis and improvements. Work together with verification and system teams, provides inputs on test plan and firmware implementation.
• Perform performance, power, area trade off analysis to achieve optimal logic efficiency.

Essential Qualifications

• Master/PhD degrees required in Computer Science, Computer Engineering or Electrical Engineering
• Verilog/System Verilog language
• 5-12 years of industry experience. in two or more fields below:
• Computer Architecture, RISC/VLIW/SIMD, CPU or GPU design
• Micro-processor architectures (ARM, Tensilica, MIPS etc.), on chip memory (ROM and SRAM) subsystem design, and on chip interconnects (AXI, ACE, AHB, APB, and Network on Chip)
• SoC peripherals (PCIe, DDR4/HBM, USB3.0, SPI, I2C, JTAG etc.)
• Lower power design, and control circuits (Power Management Units,). Knowledge in CPF/UPF flows, power gating, voltage scaling, clock gating
• Experienced with finite state machine control logic, data path logic micro architecture Design, Verilog implementation, linting. Familiar with performance vs. power trade off analysis.
• Highly motivated and self-disciplined. Strong verbal and oral communications skills. Strong team work skills, and ready to take technical leadership.

Preferred Requirements

• Good knowledge on full IC design/implementation flow, from architecture to wafer fabrication.
• Familiar with ASIC or FPGA Synthesis tools, Static Timing Analysis tools (Tempus or PrimeTime), and Logic Equivalence Checking tools.
• Scripting skills(Perl, Makefile, Python, TCL)
• FPGA prototyping experience.